Say NO to the Paywall of PCI-E Bifurcation

The Paywall of PCI-E Bifurcation

PCI-E provides CPUs the ability to connect with fast devices, like >10 Gbps networks, NVMe SSD, etc. Especially for the usage of workstations or servers, the number PCI-E slots means a lot. As a result, Xeon CPUs and server-level MBs provide more PCI-E slots than on the consumer level. On the other hand, the number of PCI-E slots on cheap MB is usually only 1 for GPU. However, those server-level MBs are more expensive.

PCI-E bifurcation is an approach to split x16 PCI-E channels into different combinations, like 8+8 or 8+4+4. Since some PCI-E devices are only in x4 or x8 speed. But unlike AMD, Intel consumer-level MBs rarely offer such an option in the BIOS, let alone the lower-end products.

Note: PLX chips can also help you like a switch, but they are also expensive.

Bypass the paywall

Let’s do some hacking to bypass such paywall. My platform is Intel Core i5-3450 + Z77, but I guess this method is also useful for any Intel CPU with public datasheet information, like 12th gen CPU[3].

First, go to the Intel ark document webpage to check the “PCI Express Configurations”, which will show all bifurcation modes that your CPU supports.

For my CPU, 16=8+8=8+4+4, which provides the opportunity to place one x8 HBA card and 2 x4 NVMe SSD in one PCI-E slot! image.png

Second, get the datasheet of your CPU, and search for bifurcation-related content. You will find the config (CFG) to control PCI-E bifurcation.

the datasheet contains infos like the definitions of LGA1155, so that we can control it manaully.


As the fig above, the value of CFG[6:5] controls bifurcation modes on my platform, and:

  • 00: 8+4+4
  • 10: 8+8
  • 11: 16

note: CFG[17:0] means 18 pins of LGA1155.

And then we search the positions of CFG pins to hard-set their values as we wish.

It shows that CFG[5] is N35, and CFG[6] is L37. So that we can find the actual physical position of CFG[5] and CFG[6].


As mentioned above, I want to set 16=8+4+4, so the values of CFG[5] and CFG[6] should be both 0. So we can ground CFG[5] and CFG[6] by connecting N35<->M35 and L37<->M37. (VSS is GND, and VCC is PWR)

I used some silver paste to make such hard strap.

Last, get a cheap PCI-E bifurcation card with clock MUX, like multiple NVMe SSDs in one PCIE card.

On my config, there is one LSI 2308 (OCP) with 2 NVMe Optane M10 in one PCI-E card. (buff叠满

Now you can enjoy multiple devices with fast connections!

Small modification, big impact. So why MB producers disable this feature?

FYI: I tried to use AMIBCP tools to modify potentially hidden options in BIOS firmware, but sadly found nothing




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