CXL + PM

CXL + PM

In modern archi, memory of devices (gragh mem) and memory of CPU is separated. Although controller of devices can access memory of CPU (DMA), the latency of PCIE is dominant. And the throughput upper bound of PCIE is too low.

So CXL is built upon PCIE 5.0 for lower latency connection over PCIE. For example, PCIE accelerator and main memory on PCI devices.

CXL 2.0 starts to support persistent memory, which can provide more persistent memory plugging in its expandable bus instead of fixed number of dimms.

interleaves across PCIE devices, and Intel uses labels to help developers to maintain the interleaving layouts.

Also, hot-plug is supported.

Global persistent flush (GPF) is a similar mechanism like ADR or eADR. no code changes are needed. But new drivers and new kernel supports are needed.

ref

  1. PM+CS Summit 2021: Persistent Memory in CXL, on youtube https://www.youtube.com/watch?v=x-OSKow9NM8, https://www.snia.org/educational-library/persistent-memory-cxl-2021
  2. Compute Express Link 标准介绍: https://www.synopsys.com/zh-cn/designware-ip/technical-bulletin/compute-express-link-standard.html
  3. About CXL™: https://www.computeexpresslink.org/about-cxl

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